The present invention relates to integrated circuit memory devices, and more particularly, to integrated circuit memory devices with redundant cells and methods of operation thereof.
Integrated circuit memory devices commonly include spare memory cells, i.e., redundant memory cells, which are used to replace primary (xe2x80x9cnormalxe2x80x9d) memory cells that are defective. In some conventional memory devices, if at least one primary memory cell connected to a column select line CSL is defective in a column redundancy scheme, the column select line CSL is replaced with a spare column select line SCSL. In other words, all memory cells connected to the column select line CSL are replaced with spare memory cells connected to the spare column select line SCSL even if only one memory cell connected to the column select line is defective.
FIG. 1 shows a conventional one-to-one dedicated column redundancy scheme. Referring to FIG. 1, input/output blocks 11 and 13 each include a plurality of memory cells, column select lines CSL11, CSL12, CSL21, CSL 22 connected to the plurality of memory cells, and spare column select lines SCSL11, SCSL12, SCSL21, SCSL22. The column select lines CSL11, CSL12, CSL21, CSL22 are connected to primary memory cells for normal operation of the primary memory cells. The spare column select lines SCSL11, SCSL12, SCSL21, SCSL22, which are connected to spare memory cells, i.e., redundant memory cells, are for used to replace defective memory cells.
The input/output block 11 includes one local input/output line LIO1 and one global input/output line GIO1, and the input/output block 13 includes one local input/output line LIO2 and one global input/output line GIO2. The local input/output line LIO1 and the global input/output line GIO1 input and output data into memory cells in the input/output block 11, and the local input/output line LIO2 and the global input/output line GIO2 input and output data into memory cells in the input/output block 13.
In the one-to-one redundancy scheme shown in FIG. 1, if a column select line CSL11 in the input/output block 11 is defective, i.e., if at least one memory cell M1 connected to the column select line CSL11 is defective, the column select line CSL11 is replaced with a spare column select line SCSL11. If a column select line CSL21 in the input/output block 13 is defective, i.e., if at least one memory cell connected to the column select line CSL21 is defective, the column select line CSL21 is replaced with a spare select line SCSL21.
In the one-to-one column redundancy scheme shown in FIG. 1, defective column select lines in a predetermined input/output block are replaced with only spare column select lines in the same input/output block. This can result in poor repair efficiency and flexibility.
FIG. 2 shows a conventional dataline column redundancy scheme. Referring to FIG. 2, in the dataline column redundancy scheme, input/output blocks 21 and 23 do not include spare column select lines. A redundant input/output block 25 includes spare column select lines.
The input/output block 21 includes one local input/output line LIO1, and the input/output block 23 includes one local input/output line LIO2. The redundant input/output block 25 also includes one local input/output line LIO3. The input/output blocks 21 and 23 and the redundant input/output block 25 share a global input/output line GIO.
Data is input into and output from memory cells in the input/output block 21 via the local input/output line LIO1 and the shared input/output line GIO, and data is input into and output from memory cells in the input/output block 23 via the local input/output line LIO2 and the shared input/output line GIO. Data is input into and output from memory cells in the redundant input/output block 25 via the local input/output line LIO3 and the shared global input/output line GIO.
In the dataline column redundancy scheme shown in FIG. 2, if column select lines CSL11 and CSL12 in the input/output block 21 are defective, the column select lines CSL11 and CSL12 are replaced with spare column select lines SCSL1 and SCSL2 in the redundant input/output block 25. If column select lines CSL21, CSL22, and CSL 23 in the input/output block 23 are defective, the column select lines CSL21, CSL22, CSL23 are replaced with spare column select lines SCSL3, SCSL4, and SCSL5 in the redundant input/output block 25.
Accordingly, in the dataline column redundancy scheme shown in FIG. 2, defective column select lines in the input/output blocks are replaced with spare column select lines in the redundant input/output block. Therefore, repair efficiency and flexibility may be improved to some extent. However, the dataline column redundancy scheme uses a generally non-uniform structure than can increase the loads of data paths for redundant input/output blocks. This can reduce access speed. In addition, if two or more column select lines corresponding to the same column address in two or more input/output blocks are connected to defective cells, repair may be impossible.
According to some embodiments of the present invention, an integrated circuit memory device includes a plurality of memory cells arranged as a plurality of blocks. Each of the blocks includes a plurality of primary memory cells that are coupled and decoupled to and from respective input/output lines responsive to a primary column select line and a plurality of redundant memory cells that are coupled and decoupled to and from respective ones of the input/output lines responsive to a redundant column select line. The device further includes a column select circuit, coupled to the primary column select lines and to the redundant column select lines, that drives a first primary column select line responsive to application of a first column address input and that drives a first redundant column select line in place of the first primary column select line responsive to application of a second column address input. The device also includes a plurality of sense amplifiers, and an input/output control circuit configurable to selectively connect input/output lines to a sense amplifier such that a primary memory cell associated with the first primary column select line is coupled to the sense amplifier responsive to the first column address input and such that a redundant memory cell associated with the first redundant column select line is coupled to the sense amplifier responsive to the second column address input.
In further embodiments, respective pluralities of input/output lines are associated with respective ones of the blocks of memory cells, and the first primary memory cell and the first redundant memory cell are in the same block of memory cells. The input/output control circuit couples the first primary memory cell and the first redundant memory cell to a sense amplifier via the plurality of input/output lines associated with the same block of memory cells. In other embodiments, the first primary memory cell and the first redundant memory cell are in respective first and second blocks of memory cells, and the input/output control circuit couples the first primary memory cell and the first redundant memory cell to a sense amplifier via first and second input/output lines associated with respective ones of the first and second blocks of memory cells.
The input/output control circuit may comprise a plurality of switches that couple and decouple the input/output lines to and from the plurality of sense amplifiers and a switch control circuit that controls the plurality of switches. The switch control circuit may be fuse programmable. Related operating methods are also discussed.